Altera FPGA

This page is dedicated to Alteras FPGA families.

Years ago, we had whole boards of logic, counters, multiplexers, drivers.
It took a long time to develop, build and debug. Now more than a board
fits into one chip, at clock rates undreamed of.

These logic devices are are incircuit programmable. The design software
'MAX+plus 2' is downloadable from their web site. Login required.
I had a look at the following families : From a certain density up, the SRAM based families become cheaper than the EEPROM based.
Currently (nov 2000) this happens at 256 flipflops.

The ACEX family

It has from 10k to 100k typical gates and is SRAM based. It therefore uses a
configuration device. This family of FPLD's was released in 2000. Therefore its
documentation is lacking a bit.
the ACEX page
The required datasheet is : ACEX datasheet
Appnotes page
Appnotes 116
The last describes the interfacing to the configuration device. There are 2 figures of note
Figure 29 is preferred, as it only uses one connector.
Application note 116 does not refer to the ACEX family, but the Flex10k family coves the case.
the mentioned pages and figures refer to the 2000 version of the AN116. The 2002 version of the AN116 changed a bit and the page numbers & figure numbers are not accurate anymore

recent projects

Octal high precision PWM

This project features 8 PWM's with high precision to control 8 RC servos at once. schematic inside
and pcb It includes a bunch of synchroneous counters plus the datalatches to auto reloading them plus
an interface to a microcontroller. Implemented into to the EP1k30, it uses less than half of the
available resouces. Built as discrete chips, it'd cover a Euro board. Implemented as FPGA, it is
reconfigured within minutes to hours to a different design.

Though this implementation is far more expensive in component costs than the discrete approach,
for low volumes it saves hours on board design and layout. Give me a month or so to come out with
such a board as product.

Programmable pulse delay generator

This project is a pockels cell timing generator and allows to extract an adjustable number of
laser pulses in sync with the laser itself. The timing pulses for the pockels cell are adjustable
with sub ns precision. It is controlled by the PC with a RS485 communication link.
Some support circuits including a microcontroller is not shown
schematic inside  pcb
The clocking rate is up too 100 MHz, quite difficult to achieve even with ECL logic, as it
contains several synchroneous counters.
A generic version is planned as product soon.


the above designs were subsequently found not to be synchroneous and changed towards being synchroneous. Meaning the schematic images are not accurate anymore. Simple reprogramming did the job.


last updated: 18.dec.2002

Copyright (99,2002) Ing.Büro R.Tschaggelar